PG Diploma in Integrated VLSI and Embedded System Design (PG-DIVESD)

NSQF level: 8

The Post Graduate Diploma in Integrated VLSI and Embedded System Design (PG DIVESD) is a 24 weeks full time programme targeted towards grooming students in the area of Embedded and VLSI designing.
  • Well established courses with excellent placement records.
  • 24-week full-time courses with 900 hours' theory/lab/project.
  • 8 hours per day theory + lab sessions on 6 days a week in most centres.
  • Continuous lab and internal assessments during the course, and
  • Centralised course-end theory exams.
  • Free textbooks/course materials provided for most modules.
  • Expert faculty from C-DAC and ICT industry with widespread domain knowledge.
  • Courses designed and developed in consultation with the domain experts in C-DAC, academia and ICT industry.
  • Syllabus regularly updated with the latest trends in the ICT industry.
  • Tutorials, hands-on and projects relevant to the standards of the ICT industry.
  • Well equipped computer labs with internet that can be accessed round the clock in many centres.
  • Training on aptitude, general English, effective communication, and interview skills.
  • Extensive placement orientation and region-wise common campus placements with excellent participation from top ICT companies.
  • Best student awards in each course.

1. Graduate in Engineering or equivalent (e.g. BE / BTech / 4-year BSc / AMIE / DoEACC B Level, etc.) in Electronics/ Computer Science/ IT or related areas, OR
2. Post Graduate in Engineering Sciences (e.g. MSc in Computer Science, IT, Electronics, etc.).
3. The candidates must have secured a minimum of 55% marks in their qualifying examination.


·         Introduction to SE

·         The software process SDLC

·         Describe and compare different SDLC models

·         Project management

·         Software implementation and maintenance

·         Structured programming, language standards

·         Software testing SQA, ISO, CMM Configuration management

·         Software process and project metrics

·         Design concepts



·         Difference between C and C+

·         Linux C++ Debugging

·         Class and Objects

·         Constructors and Destructors

·         Inheritance

·         Multiple Inheritances

·         Friend functions and Classes

·         Polymorphism

·         Overloading functions

·         Copy Constructors

·         Run Time Polymorphism

·         Virtual Functions

·         Class and Function Templates

·         Exception Handling

·         Namespaces


Introduction to Data Structures

·         Algorithms and Abstract data types, Complexity of Algorithms

·         Linked lists – types, implementation and applications

·         Stacks – Implementation and applications

·         Queues – types, implementation and applications

·         Various Searching and Sorting Algorithms

·         Trees – types, implementation and applications

·         Graphs – implementation and applications



·         System Components/Services

·         Introduction to Process Management

·         Multiprogramming, threading, tasking and processing

·         CPU Scheduling

·         Basic concept

·         Scheduling criteria

·         Scheduling Algorithm

·         Multi-Process Scheduling

·         Real Time Scheduling System Components/Services

·         Process Synchronization

·         Semaphores

·         Critical Region

·         Monitors

·         Deadlocks

·         Deadlock Characterization

·         Method for handling deadlocks

·         Deadlock prevention

·         Deadlock Avoidance

·         Introduction to memory management

·         Logical Address

·         Physical Address

·         Swapping

·         Memory Management

·         Contiguous Allocation

·         Paging

·         Segmentation

·         Segmentation with paging

·         Virtual Memory Pages

·         Demand Paging

·         Page Replacement

·         Page-Replacement Algorithme

·         Thrashing

·         File-System Interface Pages (337-360)

·         Direct Memory Access Pages (406-420)

·         Application I/O Interface

·         Kernel I/O Subsystem

·         Secondary –Storage Structure Pages (431-444)

·         Disk Structure

·         Disk Scheduling

·         Disk Management

·         Swap-Space Management

·         Disk Reliability

·         Network Structure

·         Motivation

·         Topology

·         Network Type

·         Distributed Operating System Pages

·         Comparison of different operating system(window NT/Linux/Unix)


Linux Shell Scripting

·         Linux command

·         Linux File System

·         Vi editor command

·         The Shell

      ·         Shell Programming 



·         File System Management – File concepts, Allocation and protection

·         Mechanisms

·         I/O and Secondary Storage Management

·         Linux Architecture and System Call interface

·         Processes & Signal API and POSIX thread API

·         IPC Mechanisms (Pipes, FIFOs, Semaphores, Shared Memory)

·         IPC Mechanisms (Message Queues and Sockets)

·         Memory Management in Linux, Interrupts and Timers

·         Disk Cache and Disk  I/O Management  



·         Introduction to Real time systems and Real Time Operating Systems

·         Real Time OS Concepts

·         Installation of RTLinux

·         RTLinux / ( Architecture, Module Concept, Linking a module with the kernel)

·         Introduction to basic kernel API

·         Real Time FIFO, Inter Process Communication between RT Task and Linux Process

·         IPC using shared memory, Mail boxes, Hard & Soft Interrupts, Interrupt Handling .


  • Linux Kernel configuration  and compilation
  • Introduction to Linux Device Model
  • Types of device drivers
  • Building and running module
  • Debugging techniques  in the kernel
  • Introduction to  Character Drivers
  • Interrupt Handling
  • PCI  Bus Architecture and Specifications
  • Introduction to USB Device Driver


·         Processor Architecture (Princeton and Harvard) RISC & CISC Microcontrollers Features & Memories

·         Internal Architecture Addressing Modes Overview Instruction Set

·         Data Movement Instructions Memory Instructions Arithmetic & Bit Operation Instructions

·         Hardware Features Reset & System Clock /Oscillators Timers, Input Capture & Output Compare Modes ,Watchdog Timer, Timer/Counter

·         Application Design Power, Oscillator & Reset Circuitry I/O Ports

·         Interfacing LED’s, Switches & LCD Parallel Interface

·         Interfacing Hardware to Microcontroller Types of ADC and DAC Example Interfacing of ADC & DAC to Microcontroller

·         Serial Interface through RS232 ,I2C

·         SPI Communication

·         CAN Interface & USB Interfacing



·         Introduction to 16/32-bit Processors

·         The ARM Architecture, Overview of ARM, Register Set and Modes

·         Introduction to Cortex M series

·          ARM Processor Core ARM7TDMI & ARM 9TDMI, Data Path and Instruction Decoding

·         ARM Instruction Set Introduction to Exceptions Conditional Execution, Branch, Branch Link and Branch Exchange

·         ARM Development Environment Assembler and Compilers Linkers and Debuggers

·         Software Interrupts Data Processing Instructions Multiple Register Transfer Instruction

·         Thumb Instruction Set Mixing ARM & Thumb Instructions

·         Architectural Support for High Level Language Data Types

·         Floating Point Data Types Expressions, Conditional Statements and Loops

·         Memory Hierarchy Memory Interfacing Memory Size & Speed Cache

·         Architectural Support for Operating System ARM System Control Coprocessor CP15 Protection Unit Registers

·         ARM MMU Architecture Synchronization Context Switching Enhanced DSP Extension


    ·         Introduction of Digital electronics

    ·         Number System

    ·         Boolean algebra

    ·         Combinational logic design, standard representation for logic functions

    ·         K- map representations and simplification for logic functions

    •   Quine-Maclinsy Method

    ·         Basic Building Block

    ·         Arithmetic Operations

    ·         Mux

    ·         D- Mux

    ·         Decoder

    ·         Encoder

    ·         Adder

    ·         Sub tractor

    ·         Sequential logic design

    ·         Flip-Flops

    ·         Application of Flip-Flops

    ·         Synchronous and asynchronous counter

    • LFSR
    • Synchronizers
    • Basics of State Machine

    ·         MOORE and MEALY FSM

    • State Reduction methodologies

    ·         Problems on State Machines

    • Timing analysis of digital Circuit


70 Hours  

·         History

·         Capabilities

·         Overview

·         Features of VHDL

·         Language abstractions

·         Entity Declaration

·         Concurrent VHDL

·         Signal assignment

·         Transport and inertial delays

·         Concurrency

·         Concurrent control statements

·         Behavior and data flow modeling

·         Data Types and synthesizable data type

·         Advanced data types

·         Subtypes

·         Multi dimensional array

·         Relational and arithmetic operators

·         Vector assignment

·         Bit string and literal

·         Slice of array

·         Sequential VHDL

·         Concurrent and sequential data processing

·         Processes

·         Sequential Control statements

·         Clocked sequential processes

·         Synchronous and asynchronous process

·         Postponed process

·         Assert and Loop Statements

·         Exit and Next Statements

·         Generate Statements

·         Libraries

·         Packages

·         Subprograms

·         Functions

·         Procedures

·         Side effects

·         Resolution Function

·         Structural VHDL

·         Components declaration and specification

·         Generic components

·         Configurations

·         State Machine

·         Moore machine

·         Mealy machine

·         State Machine Coding Style

·         State machine with clocked output

·         Different level of test benches



·         Introduction and overview of VERILOG

·         History and major capabilities

·         Development flow and Verilog modules

·         Description of different modeling

·         Gate Level Modeling

·         Structural design

·         Data flow Modeling

·         Behavioral Modeling

·         Simulation of the design.

·         Language element, identifiers, comments, format,

·         System task

·         Compiler directives

·         Data types: Net, Wire, wor and trior nets, wand and triand nets,    Reg,  vector and scalar nets

·         Operators: Arithmetic and logical, signed and unsigned operators, conditional operator, shift operator, concatenation operator, bit wise operator, Logical operator, Equality Operater,Relational operator, Reduction Operator

·         Gate level modeling

·         Multiple input output gates

·         Tri state gates

·         Array of instance and implicit nets

·         Structural statement

·         Module instantiation, unconnected ports, external ports and other examples

·         Data flow modeling, continuous assignment

·         Net declaration assignment

·         Delays and net delays

·         Behavioral modeling

·         Procedural construct

·         Initial statement

·         Always statement

·         Timing control

·         Delay control

·         Event control

·         Sequential statement

·         Parallel block statement

·         Conditional statement

·         Blocking and Non-Blocking Statements

·         Loops in verilog

·         Switch level Modeling

·         Task and Function

·         Introduction to User defined primitives (UDP’s)

·         Combinational UDP’s

·         Sequential UDP’s

·         Level triggered UDP’s

·         Edge triggered UDP’s

  • “Specify block” and example
  • “defparam” and its example
  •    FSM Modeling
  •   Mealy and Moore Model
  • PLI overview


·         An Introduction to verification

·         Types of verification

·         Code Coverage, Functional coverage

·         Introduction to System Verilog

·         Data Types, Operators, Arrays

·         Oops concepts in system verilog

·         Task and Function in System verilog

·         System Verilog Assertions


15 Hours  

·         Introduction of MOS device

·         N- Mos

·         P-Mos

·         CMOS

·         Structure of MOS cells

·         Threshold Voltage

·         CMOS Inverter DC Characteristics

·         Device sizing

·         Ratioed Logic

·         Non ratioed logic

·         Latch Up effect

·         Body Effect

·         Channel Length Modulation

·         CMOS as a switch

·         Noise Margin

·         Capacitance Estimation

·         Rise and fall times

·         Power dissipation

·         Design of complex circuit

·         Fabrication steps


  • Synthesis Flow
  • Libraries
  • IP Cores
  • Synchronous Vs Asynchronous Designs
  • Clock and Reset Designs
  •   Synthesis basic
  •    Logic Synthesis
  •   Design constraints
  •   Translation
  •    Optimization
  •    Logic Duplication 
  •    Technology mapping
  •    Design Partitioning
  •    Resource sharing
  •      Pipelining
  •     Synthesis of sequential and Concurrent Statements
  •     Difference between synthesis and simulation result
  •     If-else Vs Case
  •     State Machine encoding
  •    Timing Fundamental
  •     Timing analysis
  •     Timing issues
  •      Critical path
  •      Slack
  •       Problems of Timing
  •       Clock skew
  •       Types of skew
  •       Design format 
  •        Reporting files
  •        Introduction to PLD’S
  •        Introduction to PAL,
  •         Introduction to PLA 
  •         FPGA architecture
  •        Comparison Of available FPGA Architecture 
  •         Memory Architecture 
  •        FPGA and logic synthesis

ASIC Design

50 Hours  

·         Introduction of ASIC Design

·         Flow Diagram

·         Specifications and

·         Schematic cell Design.

·         Design Rule Checks,

·         Micron Rules

·         Lambda rules of the design

·         Fabrication methods of circuit elements

·         Layout design of different cells

·         Diff. Library cell designing, NAND, NOR, NOT, X-OR etc

·         Circuit Extraction

·         Electrical rule check

·         LVS

·         Post-layout Simulation

·         Parasitic extraction

·         Antenna effect

·         Electro migration effect

·         Body effect

·         Inductive and capacitive cross talk

·         Drain punch through, etc.

·         Design format

·         Timing analysis

·         Back notation

·         Post layout simulation

·         Spice simulation Analysis of analog and digital circuits, circuit elements, AC and DC analysis.

·         Transfer Characteristics, Transient responses, Noise analysis of current and voltage

·         DFT Guideline

·         Test Pattern

·         BIST



120 Hours  

The Course fees for the PG-DIVESD course is Rs. 80, 000/- (Rupees Eighty Thousand only) exclusive of Service Tax as applicable by Government of India.

The Service Tax is @ 14% applicable from August 2015 batch and amounting to Rs. 11,200/- which has to be paid by the candidate.

The course fee is to be paid in two installment as per the schedule mentioned in the website. The first installment of Rs. 10,000/- has to be paid during the counseling round and Second installment of course fees Rs. 70,000/- and Service Tax of Rs. 11,200/- totaling to Rs. 81,200/- before the course commencement.

The PG DIVESD course is designed keeping in view the current and future manpower needs of the industry. The course is well regarded by industry recruiters as assured source of well trained and high quality manpower. As a result, in the last years campuses our students have secured good placement in top ranking Embedded as well as VLSI design companies.

The Placement cell at the respective centres actively coordinates Campus Interviews for all the students. The students should note that the selection is solely governed by the requirements and recruitment policies of the various companies visiting our centres for campus recruitment. The centres only catalyse the process of bringing the companies to the campus and enable students to go through the campus recruitment process.