10 Gbps Ethernet MAC IP Core

10 Gbps Ethernet MAC IP Core

Brief Description

The 10GbE MAC core is compliant with IEEE802.3-2008 (802.3ae) specifications. The core is designed to support different configuration modes controlled by core's register file. The 10GbE MAC core has a data path of 64 bits. The core has AXI-4 streaming user application interface. The application interface is designed as a 64-bit bus operating at 156.25MHz. The core also provides AXI-4 Lite interface to read/write configuration registers for control and configuration of the 10GbE MAC.

Main uses and domain

  • Packet capture, processing and playback
  • Network monitoring and analysis
  • Packet filtering, slicing, tagging and indexing
  • Physical layer validation of multi-lane interfaces
  • Network traffic generator
  • Layer1/Layer2 10G/40G Ethernet Tester
  • Network Jammer
  • Ethernet protocol Analyzer

Features and Technical Specifications

  • Compliant with IEEE 802.3ae specification with preamble/SFD generation, frame padding, CRC generation and checking on transmit and receive respectively.
  • XGMII Interface operating at 156.25MHz.
  • Implements reconciliation layer functionality with start and terminal control character alignment, error control character and fault sequence insertion and detection.
  • Supports IEEE 802.3 XON-XOFF Pause Frame generation and termination for traffic flow control.
  • Pause frame generation additionally controllable by user application.
  • Supports 802.3bd specification with ability to generate and recognize PFC pause frames (Optional).
  • Supports Deficit Idle Count (DIC) mechanism to maintain average 12 byte IFG.
  • Padding of frames if the size of frame is less than 64 bytes.
  • Performs RS functionality by inserting proper control characters as specified by IEEE 802.3ae specifications.
  • Programmable length for checking the length of received frames (Optional).
  • Automatic generation of FCS/PAD during transmission on per frame basis.
  • Optional Forwarding of CRC.
  • Status signals available with each frame on the user interface providing information such as error information.
  • Internal XGMII Loop-back (Optional).
  • Supports Jumbo frames.
  • Configurable Transmit and Receive FIFOs.
  • Provides AXI-4 streaming user application interface with 64-bit bus operating at 156.25MHz.
  • Provides AXI-4 Lite interface to read/write configuration registers for control and configuration of the 10GbE MAC.

Platform required (if any):

10 Gbps Ethernet MAC IP core can be targeted for FPGA based systems

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Contact Details for Techno Commercial Information

viviand[at]cdac[dot]in / david[at]cdac[dot]in