Important dates

Submission site open	September 1, 2026
Paper deadline	October 1, 2026
Author Notification	November 6, 2026
Camera ready papers	November 13, 2026
Workshop	December 16, 2026

Workshop Details

Co-located with HiPC 2026, this half-day workshop will be held in Bangalore, India.

Workshop scope

The International Workshop on RISC-V for High-Performance Computing (RISCV-HPC) aims to bring together researchers, system architects, software developers, application Scientists, industry practitioners and HPC users to advance the adoption of RISC-V in High-Performance Computing (HPC).

RISC-V is an open, royalty-free Instruction Set Architecture (ISA) that enables innovation in processor design while fostering a shared and open software ecosystem. Its open and standardized architecture has led to the rapid development of a diverse range of processors and accelerators tailored to different computing domains. Although RISC-V has achieved widespread adoption across embedded, AI and edge computing, its application in HPC is still emerging.

Recent advances in high-performance RISC-V processors, vector extensions, accelerator technologies and system software have made RISC-V an increasingly attractive platform for next-generation HPC systems. These developments provide new opportunities for scalable computing, scientific applications, compiler and runtime optimization, operating system support and heterogeneous computing environments.

The open nature of the RISC-V ecosystem also enables the global HPC community to actively influence the future evolution of the architecture, software stack and development tools. A common and standards-based ecosystem including compilers, operating systems, runtime libraries and development frameworks promotes software portability across diverse ISC-V platforms while encouraging collaboration between academia, research laboratories, and industry.

This workshop provides a dedicated forum for presenting cutting-edge research, sharing deployment experiences, discussing software ecosystem developments, and exploring future directions for RISC-V in HPC. Through keynote presentations, peer-reviewed technical papers, invited talks, and interactive discussions, the workshop aims to strengthen collaboration between the RISC-V and HPC communities and accelerate the adoption of open computing technologies in future supercomputing systems.

Call for papers

We invite original research papers describing novel contributions in RISC-V technologies for High-Performance Computing.

Topics of Interest

Topics include, but are not limited to

• RISC-V processor architecture for HPC
• Vector extensions and accelerator technologies
• Compiler and toolchain development
• Runtime systems and middleware
• Operating systems and virtualization
• Performance evaluation and benchmarking
• HPC applications and optimization
• Parallel programming models
• Storage systems and I/O frameworks
• AI and Machine Learning on RISC-V
• Heterogeneous computing
• Security, reliability and resilience
• Open-source software ecosystem

We welcome

• Short paper: 4 pages (excluding references, figures, tables)
• Full Paper: minimum 6 (excluding references, figures, tables) and up to 10 pages (including references, figures, tables)

Paper submission

Workshop paper submissions should follow the IEEE conference template (double-column format, 10-pt font on 8.5″×11″ pages). The templates are available here:https://www.ieee.org/conferences/publishing/templates.html.

Authors are invited to submit original, unpublished work that is not under review elsewhere. All submissions will undergo a single-blind peer-review process.

Accepted papers presented at the RISCV-HPC 2026 Workshop will be published in the HiPC 2026 Workshop Proceedings (HiPCW 2026) with a separate ISBN. Eligible papers will subsequently be submitted for inclusion in the IEEE Xplore Digital Library, subject to IEEE publication policies.

At least one author of each accepted paper must register for HiPC 2026 and present the paper in person at the workshop for it to be included in the conference proceedings.

Submission link :

TBA

Organisation

Organising committee

• Sanjay Wandhekar, C-DAC, India
• Ashish Kuvelkar, C-DAC, India
• Yogeshwar Sonawane, C-DAC, India
• Surendra Billa, C-DAC, India
• Nick Brown, EPCC, University of Edinburgh, UK
• Teresa Cervero, BSC, Spain

Program committee

• Nick Brown, EPCC, University of Edinburgh, UK
• Teresa Cervero, BSC, Spain
• Manolis Marazakis, Forth, Greece
• Sanjay Wandhekar, C-DAC, India
• Madhu Mutyam, IIT Madras, India
• Ashish Kuvelkar, C-DAC, India
• Neel Gala, InCore Semiconductors, India
• Filippo Mantovani, BSC, Spain
• Yogeshwar Sonawane, C-DAC, India
• Sujay Deb, IIIT Delhi, India
• Surendra Billa, C-DAC, India
• Madhura Purnaprajna, AMD, India

For all queries, please contact:riscvhpc[at]cdac[dot]in