| Name of the Post | Project Engineer ( 0-5 years' experience ) |
| Specialization/ Domain | Faculty |
| No. of Requirement | 1 |
| Location | Pune |
| Qualification |
First Class B. E. / B. Tech. in Comp/IT/ Electronics/ Electronics & Telecommunication/communication OR First Class MCA OR ME / M. Tech in Comp/IT/ Electronics/ Electronics & Telecommunication/communication |
| Post Qualification relevant Experience. | BE/B. Tech/ MCA/ME/ M. Tech – Fresher’s can apply |
| Age | 37 years as on last date of application |
| Skill Sets | System Architecture, Verilog HDL,HDL Simulation and Synthesis, System Verilog, Verification using UVM, CMOS VLSI and Aspects of ASIC Design |
| Job Profile | Delivering lab sessions for the PG Diploma Courses |
| CTC per Annum | *As per the industry standards based on qualification, experience, expertise, role etc. |
| Apply Now |
*C-DAC reserves the right w.r.t. to the pay to be offered to selected candidates based on the norms of C-DAC.
Human Resource Department
Centre for Development of Advanced Computing (C-DAC)
Innovation Park 34/1, Panchavati, Pashan
Pune - 411 008