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PG Diploma In VLSI Design (PG-DVLSI)

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PG-DVLSI is a pioneering course offered by C-DAC to assist engineers who wish to gain theoretical as well as practical knowledge in the field of Very Large Scale Integration (VLSI) design. It will also prepare them to keep pace with the changing trends of VLSI technology and the requirements of an ever-growing VLSI design industry. The entire course syllabus, courseware, teaching methodology and the course delivery have been derived from the rich research and development background of C-DAC, which has a legacy of designing the PARAM range of supercomputers.

The educational eligibility criteria for PG-DVLSI course is:

  • Graduate in Engineering (10+2+4 or 10+3+3 years) in IT / Computer Science /      Electronics / Telecommunications / Electrical / Instrumentation, OR 
  • M.Sc. /M.S. (10+2+3+2 years) in Computer Science, IT, Electronics. 
  • The candidates must have secured a minimum of 55% marks in their qualifying    examination.

 

PG-DVLSI course will be delivered in fully PHYSICAL mode. The total course fee and payment details is as detailed herein below:

The total course fee is INR. 90,000/- plus Goods and Service Tax (GST) as applicable by Government of India (GOI).

The course fees for PG-DVLSI has to be paid in two installments as per the schedule.

  • First installment is INR. 10,000/- plus Goods and Service Tax (GST) as applicable by GOI.
  • Second installment is INR. 80,000/- plus Goods and Service Tax (GST) as applicable by GOI.

The course fee includes expenses towards delivering classes, conducting examinations, final mark-list and certificate, and placement assistance provided.

The first installment course fee of Rs 10,000/- + GST on it as applicable at the time of payment is to be paid online as per the schedule. It can be paid using credit/debit cards through the payment gateway. The first installment of the course fees is to be paid after seat is allocated during counseling rounds.

The second installment of the course fees is to be paid before the course commencement through NEFT.

NOTE: Candidates may take note that no Demand Draft (DD) or cheque or cash will be accepted at any C-DAC training centre towards payment of any installment of course fees.

   Combinatorial Logic Design, Sequential Logic Design: State machines, Counter Design, Advanced Design Issues: metastability, noise margins, power, fan-out, design rules, skew, timing considerations, Frequency divide Hazards. Asynchronous State Machine: Cycle stealing using latch in synchronous circuits, Interfacing Asynchronous data flow, Asynchronous FIFO design, Asynchronous to Synchronous Circuit Interaction, Case study of digital design circuits.    

   System Building Blocks: Computer Architecture, Memory Architectures, Introduction to SPI, I2C, UART, eSPI, USB.
FPGA Architecture: Architecture study of some popular FPGA families (Ultra Scale architecture), Detailed study of a AMD-Xilinx high end FPGA family, Architecture of Microcontrollers in FPGA (ARM), The backend tools, Integrating non-HDL modules: Building macros, Introduction to System on Chip (SOC), Multicore Architecture.

   Introduction to C, Arrays, Functions, Strings, Structures & unions, Introduction to C++, Classes & Objects, Inheritance, Class and Function Templates, Exception Handling, Namespaces   

   Linux Commands, Linux File System, Vi editor, The Shell, Shell Programming, Basics of  TCL scripting, Introduction to Python, Operator and Expressions, Numbers, Strings, Lists, tuples, dictionary, standard I/O operations, functions, regex, OOPS concepts 

   Module components, Data types, Operators, Modeling concepts ,Gate level Modeling, Data Flow Modeling, Behavioral modeling,  Task and Functions, Compiler Directives, Specify block and Timing checks, Verification and Writing test benches, UDP, VCD, PLI, Introduction of FSMD   

   HDL Flow, The concept of Simulation, Types of simulation, HDL Simulation and Modeling, Simulation Vs Synthesis result, The Synthesis Concept, Synthesis of high level constructs, Timing Analysis of Logic circuits, Clock Skew, Clock Jitter, Combinatorial Logic Synthesis, State machine synthesis, Efficient coding styles, Partitioning for synthesis, Pipelining, Resource sharing, Optimizing arithmetic expressions, The Simulation and Synthesis Tools, FPGA synthesis and implementation. 

   Introduction of MOS devices: N-MOS, P-MOS and CMOS, Structure of MOS cells, Threshold Voltage, CMOS Inverter Characteristics, Device sizing, CMOS combinational logic design, Design of Basic gates, transmission gates and Design of complex logic circuit, Latch Up effect, Body Effect, Channel Length Modulation, CMOS as a switch, Noise Margin, Rise and fall times, Power dissipation, Overview of CMOS fabrication steps, Sequential CMOS logic, Introduction to FinFET technology.
Introduction of Application Specific Integrated Circuit (ASIC) Design Flow: An overview of Backend VLSI Design Flow – Libraries, Floorplanning, Placement, Routing, Verification, Testing. Specifications and Schematic cell Design, Spice simulation, circuit elements, AC and DC analysis, Transfer Characteristics, Transient responses, Noise analysis of current and voltage, Design Rule, Micron Rules, Lambda rules of the design and design rule check, Fabrication methods of circuit elements, Layout design of different cells, Circuit Extraction, Electrical rule check, Layout Vs. Schematic (LVS), Post-layout Simulation and Parasitic extraction, Different design Issues like Antenna effect, Electro migration effect, Body effect, Inductive and capacitive cross talk and Drain punch through, etc., Design format, Timing analysis, Back notation and Post layout simulation, DFT Guideline, Test Pattern and Built-in Self Test (BIST), ASIC design implementation.

  

Origins, Overview, Need and Importance, SystemVerilog Declaration Spaces, Data types, Arrays , structure, union,  Procedural Blocks and Statements, Task and function, Introduction to Verification, Types of verification, Code coverage, Introduction to task & functions in SystemVerilog, OOPs Terminology, Implementation of OOPs Concepts in SystemVerilog, Randomization, Case Studies, Assertions property, Assertions Time, Functional Coverage, FSMD methodologies and working principles, Verilog Regions, Case Studies

  
Introduction to Universal Verification Methodology (UVM), Transaction, Test bench & its component, UVM class factory overview, UVM reporting, Device Under Test (DUT) and its connection with environment, Scoreboards, coverage, predictors, monitors, Hierarchy in UVM, Factory Overrides, Interfaces in UVM, Configuration, Introduction of sequences
Multiple Sequences configuration, UVM register Model, RM & its use in verification, RM integration, TLM (Transaction Level Modelling).

       

  
 

After completion of course students will be able to develop Field-Programmable Gate Array (FPGA) implementations, Application-Specific Integrated Circuit (ASIC) designs, CMOS design and SoCs in VLSI industry as VLSI designer/ chip designer. Students will also be able to develop a programmable chip using verilog and system verilog languages.

 

C-DACs - Advanced Computing Training School
Address
:
Plot No. 6 & 7, Hardware Park, Sy No. 1/1, Srisailam Highway, Pahadi Shareef Via Keshavagiri (Post), Hyderabad
Andhra Pradesh 500016
Telephone
:
7382053731 / 2
Contact Person
:
Mr. Sharanabasappa , Senior Technical Officer
Fax
:
e-Mail
:
cdachyd[at]cdac[dot]in
Courses
:
PG-DAC, PG-DVLSI, PG-DESD, PG-DSSD, e-DASSD, PG-DASSD, PG-DBDA, e-DITISS
C-DACs - Advanced Computing Training School
Address
:
Plot No. 6 & 7, Hardware Park, Sy No. 1/1, Srisailam Highway, Pahadi Shareef Via Keshavagiri (Post), Hyderabad
Telangana 500005
Telephone
:
040-23737127
Contact Person
:
Mr.Sharanabasappa, Senior Technical Officer
Fax
:
040-2374 3382
e-Mail
:
cdachyd@cdac.in
Courses
:
PG-DITISS

C-DACs - Advanced Computing Training School
Address
:
B-30, Sector 62, Institutional Area, Noida
Uttar Pradesh 201307
Telephone
:
9711770748, 0120-2210800, Ext 92
Contact Person
:
Mr. Ravi Payal
Fax
:
0120-3063374
e-Mail
:
ravipayal[at]cdac[dot]in
Courses
:
PG-DAC, PG-DVLSI, PG-DGi, PG-DESD, PG-DITISS, PG-DAI, PG-DBDA

C-DAC Patna
Address
:
14th Floor, Biscomaun Tower,West Gandhi Maidan Patna
Bihar 800001
Telephone
:
0612-2219020/1
Contact Person
:
Mr. Prince Raj
Fax
:
e-Mail
:
infocdacpatna[at]cdac[dot]in
Courses
:
PG-DAC, PG-DVLSI, PG-DESD, PG-DITISS, PG-DAI, PG-DFBD, PG-DBDA

C-DAC's Advanced Computing Training School
Address
:
C-DAC Innovation Park Sr. No. 34/B/1 Panchvati, Pashan Pune
Maharashtra 411008
Telephone
:
020-25503134/136/107
Contact Person
:
Mr. Parimal Wagh
Fax
:
NA
e-Mail
:
acts[at]cdac[dot]in
Courses
:
PG-DAC, PG-DVLSI, PG-DESD, PG-DITISS, PG-DAI, PG-DBDA, PG-DIoT , PG-DHPCAP, PG-DHPCSA

Q.    What is the Eligibility for PG-Diploma in VLSI Design?  

A.    The eligibility criteria for PG-DVLSI design is candidate holding any one of   the following degrees 

 

  • Graduate in Engineering (10+2+4 or 10+3+3 years) in IT / Computer Science / Electronics / Telecommunications / Electrical / Instrumentation. OR 
  • M.Sc /    M.S (10+2+3+2 years) in Computer Science, IT, Electronics.
  • The candidates must have secured a minimum of 55% marks in their qualifying examination. 

 

Q.    What is the selection criterion?  

A.  The selection process consists of a C-DAC Common Admission Test (C-CAT).

 

Q.    What is Fee of course? 

A.   The fees for the PG-DVLSI course is Rs. 90,000/- (Rupees Ninety  Thousand   only) plus GST as applicable by GOI.

 

Q.    When the course does commence?  

A.   Twice in a year, in the month of September and March. Admission Process   will start in  month of July and December respectively every year.

 

Q.    Duration of the course?  

A. 24 weeks approximately full-time course of total 900 hours of Theory + Practical + project work.

 

Q.   Infrastructure Facilities available?  

A.   Fully equipped classrooms capacity to accommodate students and state-of-art labs to explore you computing skills

 

Q.    Hostel & Canteen facility available?  

A.   Accommodation for out station candidates is facilitated by some of centers.   Please refer Admission Booklet.

 

 

Q. What is the medium of instruction for PG Diploma Courses?                                        

A. The medium of instruction for the PG Diploma Courses is English.

 

Q.    Revision of the course contents, is it every six months?  

A.   The course contents are revised according to the real world needs and when   found relevant to the market demands.

 

Q.   Do you have centralized placement cell?  

A. Yes, we do have a Centralized national level Common Campus Placement Programme (CCPP) spread across five regions where the respective centers actively coordinate the task of organizing the campus interviews for all the students.

 

Q.    What is the value of the course in the international market?  

A.   The course has been a trend-setting course due to its unique curriculum and   the opportunities that it generates; hence it gives the edge over above for the   students and gives an international edge.

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