Combinatorial Logic Design, Sequential Logic Design: State machines, Counter Design, Advanced Design Issues: metastability, noise margins, power, fan-out, design rules, skew, timing considerations, Frequency divide Hazards.

Asynchronous State Machine- cycle stealing using latch in synchronous circuits, Interfacing Asynchronous data flow, Asynchronous FIFO design, Case study of digital design circuits

System Building Blocks: Computer Architecture, Memory Architectures, Introduction to a system bus (PCI- Express), Introduction to peripheral bus (USB), and Introduction to a LAN (Ethernet)

FPGA Architecture: Architecture study of some popular FPGA families (Ultra Scale architecture), Detailed study of a Xilinx high end FPGA family, Architecture of Microcontrollers in FPGA (ARM), The backend tools, Integrating non-HDL modules: Building macros, Introduction to System on Chip (SOC) 

Introduction to C, Arrays, Functions, Strings, Structures & unions, Introduction to C++, Classes & Objects, Inheritance, Class and Function Templates, Exception Handling, Namespaces

Introduction to HDL, VHDL Flow, Language constructs, Concurrent constructs, Sequential Constructs, Subprogram, Packaging

The concept of Simulation, Types of simulation, HDL Simulation and Modeling, The Synthesis Concept, Synthesis of high level constructs, Timing Analysis of Logic circuits, Combinatorial Logic Synthesis, State machine synthesis, Efficient coding styles, Hierarchical and flat designs, Constraining designs, Partitioning for synthesis, Pipelining, Resource sharing, Optimizing arithmetic expressions, Design reuse, The Simulation and Synthesis Tools, FPGA synthesis and implementation

Data types, Modeling concepts, Task and Functions, Specify block and Timing checks, Verification and Writing test benches

Introduction of MOS device: N-Mos, P-Mos and CMOS, Structure of MOS cells, Threshold Voltage, CMOS Inverter Characteristics, Device sizing, Rationed and non rationed logic, CMOS combinational logic design, Design of Basic gates, transmission gates and Design of complex logic circuit, Latch Up effect, Body Effect, Channel Length Modulation, CMOS as a switch, Noise Margin, Capacitance Estimation, Rise and fall times, Power dissipation and Design of complex circuit fabrication steps.

Introduction of Full custom and semi-custom Application Specific Integrated Circuit (ASIC) Design Flow and Flow Diagram : Specifications and Schematic cell Design, Spice simulation Analysis of analog and digital circuits, circuit elements, AC and DC analysis, Transfer Characteristics, Transient responses, Noise analysis of current and voltage, Design Rule, Micron Rules, Lambda rules of the design and design rule check, Fabrication methods of circuit elements, Layout design of different cells like Diff. Library cell designing, NAND, NOR, NOT, X-OR etc., Circuit Extraction, Electrical rule check, Layout Vs. Schematic (LVS), Post-layout Simulation and Parasitic extraction, Different design Issues like Antenna effect, Electro migration effect, Body effect, Inductive and capacitive cross talk and Drain punch through, etc., Design format, Timing analysis, Back notation and Post layout simulation, DFT Guideline, Test Pattern and Built-in Self Test (BIST), ASIC design implementation

Introduction to Verification, Types of verification, Code coverage, Introduction to SystemVerilog, Introduction to task & functions in SystemVerilog, OOPs Terminology, Implementation of OOPs Concepts in SystemVerilog, Randomization, Case Studies, Assertions property, Assertions Time, Functional Coverage, Case Studies

Linux Commands, Linux File System, Vi editor, The Shell, Shell Programming, Perl, Basic of tcl/tk scripting

Introduction to Universal Verification Methodology (UVM), Transaction, Test bench & its component, UVM class factory overview, UVM reporting, Device Under Test (DUT) and its connection with environment, Scoreboards, coverage, predictors, monitors, Hierarchy in UVM, Factory Overrides, Interfaces in UVM, Configuration, Introduction of sequences

Multiple Sequences configuration, UVM register Model, RM & its use in verification, RM integration, TLM (Transaction Level Modelling)