PGD Courses Brochures

PG Diploma In VLSI Design (PG-DVLSI)

NSQF level: 8

The dynamic curriculum of VLSI fits perfectly with the career aim of working professionals, graduate and post graduate students. The below mentioned focus areas intend to help them to be future-proof and remain relevant for the rapidly evolving Semiconductor technology space. PG-DVLSI course focus on the following:

To provide rigorous foundation in MOS and CMOS digital circuits, System Building Blocks and FPGA architecture and train the students in transistor budgets, clock speeds and the growing challenges of power consumption and productivity
Understand behavioral and RTL modelling of digital circuits, design combinational and sequential circuits using Verilog HDL.
Verify and design the digital circuit by means of Computer Aided Engineering tools that involves programming with the help of Verilog HDL
To simulate, synthesize, and program the designs on a development board.
To verify that a design meets its timing constraints, both manually and through the use of computer aided design tools.
Gain the ability to analyze, design, and implement VLSI Systems. Learn to apply modern skills, techniques, and industry tools to create VLSI Circuits and Systems.
To undertake industrial research projects for the development of future solutions in the domain of Verilog Scale Integration to make an impact in the technological advancement.

Graduate in Engineering (10+2+4 or 10+3+3 years) in IT / Computer Science / Electronics / Telecommunications / Electrical / Instrumentation, OR
M.Sc /M.S. (10+2+3+2 years) in Computer Science, IT, Electronics with Mathematics in 10+2.
The candidates must have secured a minimum of 55% marks in their qualifying examination.

The total fees of the course is Rs. 76,500/- plus Goods and Service Tax (GST) currently 18%.

The course fees has to be paid in two installment as per the schedule.

First installment is Rs. 10,000/- plus Goods and Service Tax (GST) currently 18%.
Second installment is Rs. 66,500/- plus Goods and Service Tax (GST) currently 18%.

Advanced Digital Design

40 Hours

Combinatorial Logic Design, Sequential Logic Design: State machines, Counter Design, Advanced Design Issues: metastability, noise margins, power, fan-out, design rules, skew, timing considerations, Frequency divide Hazards. Asynchronous State Machine: Cycle stealing using latch in synchronous circuits, Interfacing Asynchronous data flow, Asynchronous FIFO design, Asynchronous to Synchronous Circuit Interaction, Case study of digital design circuits.

System Architecture

36 Hours

System Building Blocks: Computer Architecture, Memory Architectures, Introduction to SPI, I2C, UART, e-SPI, Ethernet , PCI-express FPGA Architecture: Architecture study of some popular FPGA families (Ultra Scale architecture), Detailed study of a Xilinx high end FPGA family, Architecture of Microcontrollers in FPGA (ARM), The backend tools, Integrating non-HDL modules: Building macros, Introduction to System on Chip (SOC)

Programming Fundamentals for Design and Verification

70 Hours

Introduction to C, Arrays, Functions, Strings, Structures & unions, Introduction to C++, Classes & Objects, Inheritance, Class and Function Templates, Exception Handling, Namespaces

Linux Shell Scripting & Python

60 Hours

Linux Commands, Linux File System, Vi editor, The Shell, Shell Programming, Basics of TCL scripting, Introduction to Python, Operator and Expressions, Numbers, Strings, Lists, tuples, dictionary, standard I/O operations, functions, regex, OOPS concepts

Verilog HDL

120 Hours

Module components, Data types, Operators, Modeling concepts ,Gate level Modeling, Data Flow Modeling, Behavioral modeling, Task and Functions, Compiler Directives, Specify block and Timing checks, Verification and Writing test benches, UDP, VCD, PLI, Introduction of FSMD

HDL Simulation and Synthesis

110 Hours

HDL Flow, The concept of Simulation, Types of simulation, HDL Simulation and Modeling, Simulation Vs Synthesis result, The Synthesis Concept, Synthesis of high level constructs, Timing Analysis of Logic circuits, Clock Skew, Clock Jitter, Combinatorial Logic Synthesis, State machine synthesis, Efficient coding styles, Partitioning for synthesis, Pipelining, Resource sharing, Optimizing arithmetic expressions, The Simulation and Synthesis Tools, FPGA synthesis and implementation.

CMOS VLSI and Aspects of ASIC Design

74 Hours

Introduction of MOS devices: N-MOS, P-MOS and CMOS, Structure of MOS cells, Threshold Voltage, CMOS Inverter Characteristics, Transfer Characteristics, Transient responses, Noise analysis of current and voltage, Noise Margin ,Rise and fall times, Power dissipation, Latch Up effect, Body Effect, Channel Length Modulation, CMOS as a switch, Device sizing, Rationed and non rationed logic, CMOS combinational logic design, Design of Basic gates, transmission gates and Design of complex logic circuit, Sequential CMOS logic, Circuit Fabrication steps, Fabrication methods of circuit elements, Introduction to FinFET technology.

Introduction of Application Specific Integrated Circuit (ASIC) Design Flow: An overview of Backend VLSI Design Flow – Libraries, Floor-planning, Placement, Routing, Verification, Testing. Specifications and Schematic cell Design, Spice simulation Analysis of analog and digital circuits, circuit elements, AC and DC analysis, Design Rules, Micron and Lambda rules, design rule check, Layout design of different cells, Circuit Extraction, Electrical rule check, Layout Vs. Schematic (LVS), Post-layout Simulation and Parasitic extraction, Different design Issues like Antenna effect, Electro migration and Body effect, Inductive and capacitive cross talk and Drain punch through, etc., Design format, Timing analysis, Back notation and Post layout simulation, DFT Guideline, Test Pattern and Built-in Self Test (BIST), ASIC design implementation.

System Verilog

90 Hours

Origins, Overview, Need and Importance, SystemVerilog Declaration Spaces, Data types, Arrays , structure, union, Procedural Blocks and Statements, Task and function, Introduction to Verification, Types of verification, Code coverage, Introduction to task & functions in SystemVerilog, OOPs Terminology, Implementation of OOPs Concepts in SystemVerilog, Randomization, Case Studies, Assertions property, Assertions Time, Functional Coverage, FSMD methodologies and working principles, Verilog Regions, Case Studies

Verification using UVM

80 Hours

Introduction to Universal Verification Methodology (UVM), Transaction, Test bench & its component, UVM class factory overview, UVM reporting, Device Under Test (DUT) and its connection with environment, Scoreboards, coverage, predictors, monitors, Hierarchy in UVM, Factory Overrides, Interfaces in UVM, Configuration, Introduction of sequences

Multiple Sequences configuration, UVM register Model, RM & its use in verification, RM integration, TLM (Transaction Level Modelling).

Effective Communication

50 Hours

Aptitude & General English

50 Hours

Project

120 Hours

After completion of course students will be able to develop Field-Programmable Gate Array (FPGA) implementations, Application-Specific Integrated Circuit (ASIC) designs, CMOS design and SoCs in VLSI industry as VLSI designer/ chip designer. Students will also be able to develop a programmable chip using verilog and system verilog languages.

Hyderabad

C-DACs - Advanced Computing Training School

Address

Plot No. 6 & 7, Hardware Park, Sy No. 1/1, Srisailam Highway, Pahadi Shareef Via Keshavagiri (Post), Hyderabad
Andhra Pradesh 500016

Telephone

7382053731 / 2

Contact Person

Mr. Sharanabasappa , Senior Technical Officer

Fax

e-Mail

cdachyd[at]cdac[dot]in

Courses

PG-DAC, PG-DVLSI, PG-DESD, PG-DSSD, e-DASSD, PG-DASSD, e-DESD, e-DAC, e-DITISS

C-DACs - Advanced Computing Training School

Address

Plot No. 6 & 7, Hardware Park, Sy No. 1/1, Srisailam Highway, Pahadi Shareef Via Keshavagiri (Post), Hyderabad
Telangana 500005

Telephone

040-23737127

Contact Person

Mr.Sharanabasappa, Senior Technical Officer

Fax

040-2374 3382

e-Mail

cdachyd@cdac.in

Courses

PG-DITISS

Nagpur

Soft Polynomials (I) Pvt. Ltd.

Address

3rd Floor, Sanganak Bhavan, North Bazar Road, Dharam Peth Extn. Gokul Peth, Nagpur
Maharashtra 440010

Telephone

0712 - 2556808, 2556809

Contact Person

Shri. S.M. Deshpande

Fax

0712 - 2556808, 2556809

e-Mail

infocdac[at]softpolynomials[dot]com, smd[at]softpolynomials[dot]com

Courses

PG-DAC, PG-DVLSI, e-DAC

Noida

C-DACs - Advanced Computing Training School

Address

B-30, Sector 62, Institutional Area, Noida
Uttar Pradesh 201307

Telephone

9711770748, 0120-2210800, Ext 92

Contact Person

Mr. Ravi Payal

Fax

0120-3063374

e-Mail

ravipayal[at]cdac[dot]in

Courses

PG-DAC, PG-DVLSI, PG-DGi, PG-DESD, PG-DITISS, PG-DAI, PG-DBDA

Pune

C-DAC's Advanced Computing Training School

Address

C-DAC Innovation Park Sr. No. 34/B/1 Panchvati, Pashan Pune
Maharashtra 411008

Telephone

020-25503134/136/107

Contact Person

Mr. Parimal Wagh

Fax

e-Mail

acts[at]cdac[dot]in

Courses

PG-DAC, PG-DVLSI, PG-DESD, PG-DITISS, PG-DAI, e-DESD, PG-DBDA, PG-DIoT, e-DAC, e-DBDA, e-DAI, e-DITISS, PG-DHPCSA

Q. What is the Eligibility for PG-Diploma in VLSI Design?

A. The eligibility criteria for PG-DVLSI design is candidate holding any one of the following degrees

Graduate in Engineering (10+2+4 or 10+3+3 years) in IT / Computer Science / Electronics / Telecommunications / Electrical / Instrumentation. OR
M.Sc / M.S (10+2+3+2 years) in Computer Science, IT, Electronics.
Mathematics in 10+2 (exempted for candidates with Diploma + Engineering).
The candidates must have secured a minimum of 55% marks in their qualifying examination.

Q. What is the selection criterion?

A. The selection process consists of a C-DAC Common Admission Test (C- CAT).

Q. What is Fee of course?

A. The fees for the PG-DVLSI course is Rs. 76,500/- (Rupees Seventy Six Thousand Five hundred only) plus GST. Due to Pandemic a 15% discount is provided for upcoming September 2021 batch.

Q. When the course does commence?

A. Twice in a year, in the month of September and March. Admission Process will start in month of July and December respectively every year.

Q. Duration of the course?

A. 30 weeks’ approximately full-time course of total 900 hours of Theory + Practical + project work.

Q. Infrastructure Facilities available?

A. Fully equipped classrooms capacity to accommodate students and state-of-art labs to explore you computing skills

Q. Hostel & Canteen facility available?

A. Accommodation for out station candidates is facilitated by some of centers. Please refer Admission Booklet.

Q. Bank loan assistance for the other centers?

A. Facility of educational loans is provided for the selected candidates, which is available at all nationalized banks.

Q. Revision of the course contents, is it every six months?

A. The course contents are revised according to the real world needs and when found relevant to the market demands.

Q. Do you have centralized placement cell?

A. Yes, we do have a Centralized Common Campus Placement Programme (CCPP) where the respective centers actively coordinate the task of organizing the campus interviews for all the students.

Q. What is the value of the course in the international market?

A. The course has been a trend-setting course due to its unique curriculum and the opportunities that it generates; hence it gives the edge over above for the students and gives an international edge.