The dynamic curriculum of VLSI fits perfectly with the career aim of working professionals, graduate and post graduate students. The below mentioned focus areas intend to help them to be future-proof and remain relevant for the rapidly evolving Semiconductor technology space. PG-DVLSI course focus on the following:
- To provide rigorous foundation in MOS and CMOS digital circuits, System Building Blocks and FPGA architecture and train the students in transistor budgets, clock speeds and the growing challenges of power consumption and productivity
- Understand behavioral and RTL modelling of digital circuits, design combinational and sequential circuits using Verilog HDL.
- Verify and design the digital circuit by means of Computer Aided Engineering tools that involves programming with the help of Verilog HDL
- To simulate, synthesize, and program the designs on a development board.
- To verify that a design meets its timing constraints, both manually and through the use of computer aided design tools.
- Gain the ability to analyze, design, and implement VLSI Systems. Learn to apply modern skills, techniques, and industry tools to create VLSI Circuits and Systems.
- To undertake industrial research projects for the development of future solutions in the domain of Verilog Scale Integration to make an impact in the technological advancement.
PG-DVLSI is a pioneering course offered by C-DAC to assist engineers who wish to gain theoretical as well as practical knowledge in the field of Very Large Scale Integration (VLSI) design. It will also prepare them to keep pace with the changing trends of VLSI technology and the requirements of an ever-growing VLSI design industry. The entire course syllabus, courseware, teaching methodology and the course delivery have been derived from the rich research and development background of C-DAC, which has a legacy of designing the PARAM range of supercomputers.
The educational eligibility criteria for PG-DVLSI course is:
- Graduate in Engineering (10+2+4 or 10+3+3 years) in IT / Computer Science / Electronics / Telecommunications / Electrical / Instrumentation, OR
- M.Sc. /M.S. (10+2+3+2 years) in Computer Science, IT, Electronics.
- The candidates must have secured a minimum of 55% marks in their qualifying examination.
PG-DVLSI course will be delivered in fully PHYSICAL mode. The total course fee and payment details is as detailed herein below:
The total course fee is INR. 90,000/- plus Goods and Service Tax (GST) as applicable by Government of India (GOI).
The course fees for PG-DVLSI has to be paid in two installments as per the schedule.
- First installment is INR. 10,000/- plus Goods and Service Tax (GST) as applicable by GOI.
- Second installment is INR. 80,000/- plus Goods and Service Tax (GST) as applicable by GOI.
The course fee includes expenses towards delivering classes, conducting examinations, final mark-list and certificate, and placement assistance provided.
The first installment course fee of Rs 10,000/- + GST on it as applicable at the time of payment is to be paid online as per the schedule. It can be paid using credit/debit cards through the payment gateway. The first installment of the course fees is to be paid after seat is allocated during counseling rounds.
The second installment of the course fees is to be paid before the course commencement through NEFT.
NOTE: Candidates may take note that no Demand Draft (DD) or cheque or cash will be accepted at any C-DAC training centre towards payment of any installment of course fees.
System Building Blocks: Computer Architecture, Memory Architectures, Introduction to SPI, I2C, UART, eSPI, USB.
Combinatorial Logic Design, Sequential Logic Design: State machines, Counter Design, Advanced Design Issues: metastability, noise margins, power, fan-out, design rules, skew, timing considerations, Frequency divide Hazards. Asynchronous State Machine: Cycle stealing using latch in synchronous circuits, Interfacing Asynchronous data flow, Asynchronous FIFO design, Asynchronous to Synchronous Circuit Interaction, Case study of digital design circuits.
Introduction to C, Arrays, Functions, Strings, Structures & unions, Introduction to C++, Classes & Objects, Inheritance, Class and Function Templates, Exception Handling, Namespaces
Linux Commands, Linux File System, Vi editor, The Shell, Shell Programming, Basics of TCL scripting, Introduction to Python, Operator and Expressions, Numbers, Strings, Lists, tuples, dictionary, standard I/O operations, functions, regex, OOPS concepts
Module components, Data types, Operators, Modeling concepts ,Gate level Modeling, Data Flow Modeling, Behavioral modeling, Task and Functions, Compiler Directives, Specify block and Timing checks, Verification and Writing test benches, UDP, VCD, PLI, Introduction of FSMD
HDL Flow, The concept of Simulation, Types of simulation, HDL Simulation and Modeling, Simulation Vs Synthesis result, The Synthesis Concept, Synthesis of high level constructs, Timing Analysis of Logic circuits, Clock Skew, Clock Jitter, Combinatorial Logic Synthesis, State machine synthesis, Efficient coding styles, Partitioning for synthesis, Pipelining, Resource sharing, Optimizing arithmetic expressions, The Simulation and Synthesis Tools, FPGA synthesis and implementation.
Introduction of MOS devices: N-MOS, P-MOS and CMOS, Structure of MOS cells, Threshold Voltage, CMOS Inverter Characteristics, Device sizing, CMOS combinational logic design, Design of Basic gates, transmission gates and Design of complex logic circuit, Latch Up effect, Body Effect, Channel Length Modulation, CMOS as a switch, Noise Margin, Rise and fall times, Power dissipation, Overview of CMOS fabrication steps, Sequential CMOS logic, Introduction to FinFET technology.
Origins, Overview, Need and Importance, SystemVerilog Declaration Spaces, Data types, Arrays , structure, union, Procedural Blocks and Statements, Task and function, Introduction to Verification, Types of verification, Code coverage, Introduction to task & functions in SystemVerilog, OOPs Terminology, Implementation of OOPs Concepts in SystemVerilog, Randomization, Case Studies, Assertions property, Assertions Time, Functional Coverage, FSMD methodologies and working principles, Verilog Regions, Case Studies
After completion of course students will be able to develop Field-Programmable Gate Array (FPGA) implementations, Application-Specific Integrated Circuit (ASIC) designs, CMOS design and SoCs in VLSI industry as VLSI designer/ chip designer. Students will also be able to develop a programmable chip using verilog and system verilog languages.
Andhra Pradesh 500016
Telangana 500005
Uttar Pradesh 201307
Bihar 800001
Maharashtra 411008
- Graduate in Engineering (10+2+4 or 10+3+3 years) in IT / Computer Science / Electronics / Telecommunications / Electrical / Instrumentation. OR
- M.Sc / M.S (10+2+3+2 years) in Computer Science, IT, Electronics.
- The candidates must have secured a minimum of 55% marks in their qualifying examination.