PGD Courses Brochures

PG Diploma In VLSI Design (PG-DVLSI)

NSQF level: 8

Download Admission Booklet

PG-DVLSI is a pioneering course offered by C-DAC to assist engineers who wish to gain theoretical as well as practical knowledge in the field of Very Large Scale Integration (VLSI) design. It will also prepare them to keep pace with the changing trends of VLSI technology and the requirements of an ever-growing VLSI design industry. The entire course syllabus, courseware, teaching methodology and the course delivery have been derived from the rich research and development background of C-DAC, which has a legacy of designing the PARAM range of supercomputers.

Graduate in Engineering (10+2+4 or 10+3+3 years) in IT / Computer Science / Electronics / Telecommunications / Electrical / Instrumentation. OR MSc/MS (10+2+3+2 years) in Computer Science, IT, Electronics.
Mathematics in 10+2 (exempted for candidates with Diploma + Engineering) OR
The candidates must have secured a minimum of 55% marks in their qualifying examination.

The total fees of the course is Rs. 90,000/- plus Goods and Service Tax (GST) currently 18%.

The course fees has to be paid in two installment as per the schedule.

First installment is Rs. 10,000/- plus Goods and Service Tax (GST) currently 18%.
Second installment is Rs. 80,000/- plus Goods and Service Tax (GST) currently 18%.

Advanced Digital Design

40 Hours

Combinatorial Logic Design, Sequential Logic Design: State machines, Counter Design, Advanced Design Issues: metastability, noise margins, power, fan-out, design rules, skew, timing considerations, Frequency divide Hazards. Asynchronous State Machine: Cycle stealing using latch in synchronous circuits, Interfacing Asynchronous data flow, Asynchronous FIFO design, Asynchronous to Synchronous Circuit Interaction, Case study of digital design circuits.

System Architecture

36 Hours

System Building Blocks: Computer Architecture, Memory Architectures, Introduction to a system bus (PCI- Express), Introduction to peripheral bus (USB), and Introduction to LAN (Ethernet)

FPGA Architecture: Architecture study of some popular FPGA families (Ultra Scale architecture), Detailed study of a Xilinx high end FPGA family, Architecture of Microcontrollers in FPGA (ARM), The backend tools, Integrating non-HDL modules: Building macros, Introduction to System on Chip (SOC)

Linux Shell Scripting & Perl

60 Hours

Linux Commands, Linux File System, VI editor, The Shell, Shell Programming, Perl, Basic of tcl/tk scripting

Programming Fundamentals for Design and Verification

70 Hours

Introduction to C, Arrays, Functions, Strings, Structures & unions, Introduction to C++, Classes & Objects, Inheritance, Class and Function Templates, Exception Handling, Namespaces

Verilog HDL

120 Hours

Data types, Modeling concepts, Task and Functions, Specify block and Timing checks, Verification and Writing test benches

HDL Simulation and Synthesis

110 Hours

The concept of Simulation, Types of simulation, HDL Simulation and Modeling, The Synthesis Concept, Synthesis of high level constructs, Timing Analysis of Logic circuits, Combinatorial Logic Synthesis, State machine synthesis, Efficient coding styles, Hierarchical and flat designs, Constraining designs, Partitioning for synthesis, Pipelining, Resource sharing, Optimizing arithmetic expressions, Design reuse, The Simulation and Synthesis Tools, FPGA synthesis and implementation

CMOS VLSI and Aspects of ASIC Design

74 Hours

Introduction of MOS devices: N-MOS, P-MOS and CMOS, Structure of MOS cells, Threshold Voltage, CMOS Inverter Characteristics, Device sizing, Rationed and non rationed logic, CMOS combinational logic design, Design of Basic gates, transmission gates and Design of complex logic circuit, Latch Up effect, Body Effect, Channel Length Modulation, CMOS as a switch, Noise Margin, Capacitance Estimation, Rise and fall times, Power dissipation and Design of complex circuit fabrication steps. Sequential CMOS logic, Introduction to FinFET technology.

Introduction of Application Specific Integrated Circuit (ASIC) Design Flow: An overview of Backend VLSI Design Flow – Libraries, Floorplanning, Placement, Routing, Verification, Testing. Specifications and Schematic cell Design, Spice simulation Analysis of analog and digital circuits, circuit elements, AC and DC analysis, Transfer Characteristics, Transient responses, Noise analysis of current and voltage, Design Rule, Micron Rules, Lambda rules of the design and design rule check, Fabrication methods of circuit elements, Layout design of different cells, Circuit Extraction, Electrical rule check, Layout Vs. Schematic (LVS), Post-layout Simulation and Parasitic extraction, Different design Issues like Antenna effect, Electro migration effect, Body effect, Inductive and capacitive cross talk and Drain punch through, etc., Design format, Timing analysis, Back notation and Post layout simulation, DFT Guideline, Test Pattern and Built-in Self Test (BIST), ASIC design implementation.

SystemVerilog

90 Hours

SystemVerilog: Origins, Overview, Need and Importance, SystemVerilog Declaration Spaces, Data types, Arrays , structure, union, Procedural Blocks and Statements, Task and function, Introduction to Verification, Types of verification, Code coverage, Introduction to task & functions in SystemVerilog, OOPs Terminology, Implementation of OOPs Concepts in SystemVerilog, Randomization, Case Studies, Assertions property, Assertions Time, Functional Coverage, Case Studies

Verification using UVM

80 Hours

Introduction to Universal Verification Methodology (UVM), Transaction, Test bench & its component, UVM class factory overview, UVM reporting, Device Under Test (DUT) and its connection with environment, Scoreboards, coverage, predictors, monitors, Hierarchy in UVM, Factory Overrides, Interfaces in UVM, Configuration, Introduction of sequences

Multiple Sequences configuration, UVM register Model, RM & its use in verification, RM integration, TLM (Transaction Level Modelling)

Effective Communication

50 Hours

Aptitude & General English

50 Hours

Project

120 Hours

After completion of course students will be able to develop field-programmable gate array (FPGA) implementations, application-specific integrated circuit (ASIC) designs, CMOS design and SoCs in VLSI industry as VLSI designer/ chip designer. Students will also be able to develop a programmable chip using verilog and system verilog languages..

Hyderabad

C-DACs - Advanced Computing Training School

Address

Plot No. 6 & 7, Hardware Park, Sy No. 1/1, Srisailam Highway, Pahadi Shareef Via Keshavagiri (Post), Hyderabad
Andhra Pradesh 500016

Telephone

040-2373 7127

Contact Person

Mr. Sharanabasappa , Senior Technical Officer

Fax

040-2374 3382

e-Mail

cdachyd[at]cdac[dot]in

Courses

PG-DAC, PG-DVLSI, PG-DESD, PG-DSSD, PG-DASSD

C-DACs - Advanced Computing Training School

Address

Plot No. 6 & 7, Hardware Park, Sy No. 1/1, Srisailam Highway, Pahadi Shareef Via Keshavagiri (Post), Hyderabad
Telangana 500005

Telephone

040-23737127

Contact Person

Mr.Sharanabasappa, Senior Technical Officer

Fax

040-2374 3382

e-Mail

cdachyd@cdac.in

Courses

PG-DITISS

Mumbai

Thakur Institute of Career Advancement

Address

C/o Thakur College of Engineering and Technology, A Block, Thakur Educational Campus, Shyamnarayan Thakur Marg, Thakur Village, Kandivali (East), Mumbai
Maharashtra 400101

Telephone

022-67308113/ 022-6730 8277

Contact Person

Dr. B. K. Mishra

Fax

022 – 28541993

e-Mail

tica[at]thakureducation[dot]org

Courses

PG-DAC, PG-DVLSI, PG-DESD, DASDM

Nagpur

Soft Polynomials (I) Pvt. Ltd.

Address

3rd Floor, Sanganak Bhavan, North Bazar Road, Dharam Peth Extn. Gokul Peth, Nagpur
Maharashtra 440010

Telephone

0712 - 2556808, 2556809

Contact Person

Shri. S.M. Deshpande

Fax

0712 - 2556808, 2556809

e-Mail

infocdac[at]softpolynomials[dot]com, smd[at]softpolynomials[dot]com

Courses

PG-DAC, PG-DVLSI, PG-DESD, DASDM

Noida

C-DACs - Advanced Computing Training School

Address

B-30, Sector 62, Institutional Area, Noida
Uttar Pradesh 201307

Telephone

0120-3063371-73

Contact Person

Mr. V.K. Sharma

Fax

0120-3063374

e-Mail

cdacacts-noida[at]cdac[dot]in

Courses

PG-DAC, PG-DVLSI, PG-DGi, PG-DESD, PG-DMC, PG-DITISS, PG-DAI, PG-DBDA, PG-DIoT

Pune

C-DAC Advanced Computing Training School

Address

C-DAC Innovation Park Sr. No. 34/B/1 Panchvati, Pashan Pune
Maharashtra 411008

Telephone

18008430222

Contact Person

Mr. Parimal Wagh

Fax

e-Mail

acts[at]cdac[dot]in

Courses

PG-DAC, PG-DVLSI, PG-DESD, PG-DITISS, PG-DAI, PG-DBDA, PG-DIoT, PG-DHPCSA

Q. What is the Eligibility for PG-Diploma in VLSI Design?

A: The eligibility criteria for PG-DVLSI design is candidate holding any one of the following degrees

Graduate in Engineering or equivalent (e.g. BE / BTech / 4-year BSc Engg / AMIE / DoEACC B Level) in IT / Computer Science / Electronics / Telecommunications / Electrical / Instrumentation. OR
Post Graduate Degree in Engineering Sciences with corresponding basic degree (e.g. MSc in Computer Science, IT, Electronics)
The candidates must have secured a minimum of 55% marks in their qualifying examination.

Q: What is the selection criterion?

A: The selection process consists of a C-DAC Common Admission Test (C-CAT).

Q: What is Fee of course?

A: The fees for the PG-DVLSI course is Rs. 80,000/- (Rupees Eighty Thousand only) plus 18% GST.

Q: When the course does commence?

A: Twice in a year in the month of August and February. Admission Process will start in month of May

and November every year.

Q: Duration of the course?

A: 24 weeks full-time course

Q: Infrastructure Facilities available?

A: Fully equipped classrooms capacity to accommodate students and state-of-art labs to explore you computing skills

Q: Hostel & Canteen facility available?

A: Accommodation for out station candidates is facilitated by some of centres. Please refer Admission Booklet.

Q: Bank loan assistance for the other centres?

A: Facility of educational loans is provided for the selected candidates, which is available at all nationalized banks.

Q: Revision of the course contents, is it every six months?

A: The course contents are revised according to the real world needs and when found relevant to the market demands.

Q: Do you have centralized placement cell?

A: Yes we do have a centralized placement programme where the respective centers actively coordinate the task of organizing the campus interviews for all the students.

Q: What is the value of the course in the international market?

A: The course has been a trend-setting course due to its unique curriculum and the opportunities that it generates; hence it gives the edge over above for the students and gives a international edge.